1. Technical Field
The present invention relates generally to computer-aided design of very-large-scale integrated circuits (VLSI). More specifically, the present invention provides a method of performing automated component placement in a hierarchically-defined semiconductor design.
2. Description of the Related Art
As integrated circuits increase in complexity and functionality, it becomes increasingly useful to adopt a hierarchical approach to their design. By “hierarchical” it is meant that the unit-level design (i.e., the design of the entire circuit—the “unit”—as a whole) is divided into smaller-scale “macro elements,” which are themselves composed of smaller, lower-level components or “cells” (which, themselves, may be comprised of even smaller, lower-level components). Hierarchical design aids in the organization of the design process and also helps to avoid unnecessary duplication of work, since a typical circuit design will likely contain multiple copies of a single macro element and will usually contain multiple copies of a single cell.
FIG. 1 provides an example of such a hierarchical design. Unit 100 is contains a plurality of macro elements 102, 104, and 106, each of which functions more or less like a “black box” for purposes of unit-level design/analysis. Each of these macro elements is itself composed of multiple cells, such as cell 107. We call cell 107 a “macro-level” cell, because it is a cell that makes up part of the design for a macro element. Macro elements 102, 104, and 106 function together as a unit by virtue of their connections to each other via their respective I/O (input/output) “pins,” which represent the “black box” input and output terminals of each macro element. For instance, in FIG. 1, macro elements 102 and 106 are connected to each other via their respective I/O pins 112 and 114, interconnection path 108, and “unit-level” cell 110, which serves as an interface (e.g., “glue logic,” in a digital circuit context) between the two macro elements. We call cell 110 a “unit-level” cell because it is not part of the “block box” design of any of the macro elements—it exists at the “unit level” but not at the “macro level.”
The basic design process in a hierarchical design, therefore, is to first design the individual macro elements (or pull them from a library of existing designs), then assemble those individually designed and tested “black boxes” into the completed design, adding any necessary interface circuitry in the form of “unit-level” cells. While this approach provides considerable benefits to the designer, a pure black-box approach may come with the cost of decreased timing efficiency of the finished design. The example provided in FIG. 1 illustrates why this may the case. If macro element 104 is treated like a true “black box,” unit-level cell 110 must reside outside of the boundaries of macro element 104, thus requiring interconnection path 108 to wind itself around macro element 104 to avoid the obstacle macro element 104 presents. This longer interconnection path introduces a certain amount of delay into the signal(s) running between macro element 102 and 106. In the best case, this added delay will merely degrade performance somewhat. However, in a timing-critical portion of a design, such a delay may prevent the design from working at all. Such a delay might be addressed by abandoning the black-box model and addressing the placement problem at a global, unit-level, but this approach also implies abandoning the many conveniences of the hierarchical design paradigm. Additionally, such global optimization can be computationally quite expensive.
What is needed, therefore, is a method of addressing critical timing issues in the context of unit-level placement/layout in a hierarchical design. The present invention provides a solution to this and other problems, and offers other advantages over previous solutions.